Some hardware description languages (HDL), for example Verilog, provide a way of expressing design unit functionality with a single process of a form similar to a logic truth table. The columns of the table represent one or more single-bit input ports plus one single-bit output port, and the rows represent combinations of input port values and value changes (edges) plus the value to place on the output port. Such a design unit is called a User Defined Primitive (UDP), and the truth table-like specification is called a UDP state table. As with a truth table, the inputs of a UDP are compared against the rows of the state table, and whichever row matches the inputs determines the output value.
In an attempt to improve performance in simulating a UDP, prior approaches specified transforming the UDP state table such that every possible combination of different input values was expanded into its own table entry. Computing the output value of the UDP then involved applying a polynomial formula to the input values to calculate a table index and looking up the output value at the indexed location in the table. Although calculating the index value is a constant time operation, the constant value is high, making the computation expensive. Also, a value change history of a net may be used to detect an edge on the signal at the input port of a UDP. Maintaining the value change history for the input signals of each UDP slows the simulation. Further impacting a desired level of efficiency is the size of the UDP state table, which grows exponentially with the number of UDP inputs. The memory devoted to storing the large UDP state table might otherwise be used to store other parts of the simulation model.